1. Field of the Invention
The present invention relates to integrated circuit technology and integrated circuit structures. More particularly, the present invention relates to integrated circuit wafers having metal interconnect lines traversing die scribe-line boundaries, integrated circuit dice having metal interconnect lines passing through scribe saw-cut lines and to methods for forming metal interconnect structures traversing scribe-line boundaries.
2. The Prior Art
A major issue relating to integrated circuit dice having metal interconnect lines passing through scribe saw-cut lines is contamination. Referring first to FIGS. 1A and 1B, respectively, a top view and a cross-sectional view of metal interconnect wiring in a portion of a prior-art semiconductor wafer at the edges of two dice disposed thereon shows a typical environment of the present invention.
In general, a structure known as the “die seal” is built at the border between the chip (outside the pads) and the scribe line area of the die. Usually the die seal consists of a substrate tap and a continuous ring of each layer of metal electrically shorted to that tap and tied to ground. This prevents chemical contaminants from seeping into the chip and damaging it during later stages of the manufacturing process, package assembly, testing, PCB assembly, and during its useful lifetime in the target application.
Specifically semiconductor wafer 10 includes a first die 12 that includes a segment 14 of interconnect wiring in a first lower metal layer disposed above a first interlayer dielectric layer 16 formed on substrate 18 and a segment 20 of interconnect wiring in a second upper metal layer disposed above a second interlayer dielectric layer 22. A passivation layer 24 is disposed above the second upper metal layer. A scribe line (dashed line 26) indicates where the first die 12 is to be separated from a second die 28 including a segment 30 of interconnect wiring in the first lower metal layer disposed above the first interlayer dielectric layer 16 and a segment 32 of interconnect wiring in the second upper metal layer disposed above the second interlayer dielectric layer 22.
A scribe seal metal region is located on first die 12 just inside scribe line 26 (to the left of scribe line 26 in FIGS. 1A and 1B). As will be appreciated by persons of ordinary skill in the art, the scribe seal metal region is formed from a portion 34 of the first lower metal layer and a portion 36 of the second upper metal layer. As shown in FIG. 1B, portion 34 of the first lower metal layer makes contact with an n+ doped region 38 in the substrate 18. A similar scribe seal metal region is located on second die 40 just inside of scribe line 26 (to the right of scribe line 26 in FIGS. 1A and 1B). The scribe seal metal region on second die 40 is formed from a portion 42 of the first lower metal layer and a portion 44 of the second upper metal layer. As shown in FIG. 1B, portion 42 of the lower metal layer makes contact between portion 36 of the lower metal layer and an n+ doped region 46 in the substrate 26. After the wafer containing dice 12 and 40 has been scribed to separate die 12 from die 40, the scribe seals in dice 12 and 40 and the overlying passivation layer 24 together act as border seals to protect the interiors of first die 12 and second die 40 from contamination.
The conventional wisdom is that metal connections that pass through the die seal can potentially serve as conduits for contamination to enter through the protective barrier of the seal, especially if these signals can be at higher voltages than the grounded substrate (as is the case in conventional CMOS circuits). Therefore, metal connections across a die seal are not used in the prior art.